1. Technical Field
The present embodiments relate to clock and data recovery (CDR) systems. More specifically, the present embodiments relate to techniques for reducing power consumption in high-frequency CDR systems.
2. Related Art
High-speed serial interfaces for point-to-point communication over a link may clock the two endpoints of the link using different clock sources. Some serial data communication standards may require the serial interface to vary its clock frequency (e.g., by using a spread spectrum clock) to reduce electromagnetic interference (EMI). The receiver endpoint of a serial interface may thus include a clock and data recovery (CDR) mechanism to recover the clock frequency over the link.
Increasing data rates for serial interface standards have resulted in corresponding increases in the clock frequencies of CDR systems. For example, a CDR mechanism for a Serial Advanced Technology Attachment (SATA) receiver may execute at roughly half the clock frequency of the data signal over the SATA link to facilitate low-latency tracking of the data signal's clock frequency. As a result, CDR mechanisms in such high-speed serial interfaces tend to consume more power than CDR mechanisms which have higher latencies and/or which operate at slower data speeds.